`timescale 1ns/1ns

module clk_divider #(
           parameter dividor = 5
       )(
           input clk_in,
           input rst_n,
           output clk_out
       );
reg [$clog2(dividor) - 1: 0] cnt;

always@(posedge clk_in or negedge rst_n)
	begin
		if (!rst_n)
			cnt <= 'd0;
		else if (cnt == dividor - 1)
			cnt <= 'd0;
		else
			cnt <= cnt + 1'b1;
	end

reg clk_a, clk_b;
always@(posedge clk_in or negedge rst_n)
	begin
		if (!rst_n)
			clk_a <= 'd0;
		else if (cnt == 'd0 | cnt == (dividor - 1) / 2)
			clk_a <= ~clk_a;
		else
			clk_a <= clk_a;
	end

always@(negedge clk_in or negedge rst_n)
	begin
		if (!rst_n)
			clk_b <= 'd0;
		else if (cnt == 'd1 | cnt == (dividor - 1) / 2+1)
			clk_b <= ~clk_b;
		else
			clk_b <= clk_b;
	end

assign clk_out = clk_a | clk_b;
endmodule
